Printed circuit boards, laminate chip carriers, and the like (referred to herein also as circuitized substrates) used in many of today's technologies must permit the formation of multiple circuits in a minimum volume or space. As indicated above, these end products typically comprise a “stack” of layers of signal, ground and/or power planes (lines) separated from each other by at least one layer of dielectric material. The circuit lines or pads, e.g., those of the signal planes, are often in electrical contact with each other by plated holes passing through the dielectric layers. The plated holes are often referred to as “vias” if internally located, “blind vias” if extending a predetermined depth within the board from an external surface, or “plated-thru-holes” (hereinafter also referred to simply as PTHs) if extending substantially through the board's full thickness. By the term “thru-hole” as used herein is meant to include all three types of such board openings.
Product complexity has increased significantly over the past few years. For example, PCBs for mainframe computers may have as many as thirty-six layers of circuitry or more, with the complete stack having a thickness of as much as about 0.250 inch (250 mils). These boards are typically designed with three or five mil wide signal lines and twelve mil diameter thru-holes. For increased circuit densification in many of today's products such as PCBs, chip carriers and the like, the industry desires to reduce signal lines to a width of two mils or less and thru-hole diameters to two mils or less. Most known commercial procedures, especially those of the nature described herein, are incapable of economically forming the dimensions desired by the industry. Known processes for fabricating PCBs, chip carriers and the like typically comprise fabrication of separate innerlayer circuits (circuitized layers), which are formed by coating a photosensitive layer or film over a copper layer of a copper clad innerlayer base material. The photosensitive coating is imaged, developed and the exposed copper is etched to form conductor lines. After etching, the photosensitive film is stripped from the copper leaving the circuit pattern on the surface of the innerlayer base material. This processing is also referred to as photolithographic processing in the PCB art and further description is not deemed necessary.
Following individual inner-layer circuit formation, a multilayer stack is formed by preparing a lay-up of innerlayers, ground planes, power planes, etc., typically separated from each other by a dielectric pre-preg typically comprising a layer of glass (typically fiberglass) cloth impregnated with a partially cured material, typically a B-stage epoxy resin. The top and bottom outer layers of the stack usually comprise copper clad, glass-filled, epoxy planar substrates with the copper cladding comprising exterior surfaces of the stack. The stack is laminated to form a monolithic structure using heat and pressure to fully cure the B-stage resin. The stack so formed typically has metal (usually copper) cladding on both of its exterior surfaces. Exterior circuit layers are formed in the copper cladding using procedures similar to the procedures used to form the innerlayer circuits. A photosensitive film is applied to the copper cladding. The coating is exposed to patterned activating radiation and developed. An etchant is then used to remove copper bared by the development of the photosensitive film. Finally, the remaining photosensitive film is removed to provide the exterior circuit layers.
Thru-holes (also often referred to as interconnects) are often used to electrically connect individual circuit layers within the structure to each other and to the outer surfaces, and typically pass through all or a portion of the stack. Thru-holes are generally formed prior to the formation of circuits on the exterior surfaces by drilling holes through the stack at appropriate locations. Following several pre-treatment steps, the walls of the holes are catalyzed by contact with a plating catalyst and metallized, typically by contact with an electroless or electrolytic copper plating solution to form conductive pathways between circuit layers. Following formation of the conductive thru-holes, exterior circuits, or outerlayers are formed using the procedure described above. It is essential that any dielectric used for the substrate must promote such hole formation.
Semiconductor chips and/or other electrical components are next mounted at appropriate locations on the exterior circuit layers of the multilayered stack, typically using solder mount pads to bond the components to the PCB. The components are often in electrical contact with the circuits within the structure through the conductive thru-holes, as desired. The solder pads are typically formed by coating an organic solder mask coating over the exterior circuit layers. The solder mask may be applied by screen coating a liquid solder mask coating material over the surface of the exterior circuit layers using a screen having openings defining areas where solder mount pads are to be formed. Alternatively, a photoimageable solder mask may be coated onto the board and exposed and developed to yield an array of openings defining the pads. The openings are then coated with solder using processes known to the art such as wave soldering.
Development of ever-increasing high speed circuitized substrates for many of today's new products (e.g., computers) has led to the exploration of new materials which would extend the electrical and thermal performance limits of the presently available technology. For high-speed applications, it is necessary to have extremely dense conductor circuitry patterning on low dielectric constant insulating material. Prepreg laminates for conventional circuit boards are traditionally made up of a base reinforcing glass fabric impregnated with a resin, also referred to by some in the industry as “FR4” dielectric material, the FR standing for Flame Retardant and the 4 for the relative value of same. Epoxy/glass laminates, used in some current products, typically contain about 40% by weight fiber glass and 60% by weight epoxy resin, and typically have a relatively high dielectric constant (Er), sometimes higher than 4.0. Such a relatively high Er in turn causes electrical pulses (signals) in adjacent signal circuit lines to propagate less rapidly, resulting in excessive signal delay time. As newer computer systems become faster, system cycle times must become shorter. Delay time contributed by signal travel within the PCB's and other circuitized substrates used in such products will become very significant; hence the need for lower Er laminate materials exists. Many products are expected to require overall Er's of 2.8 or below. In addition the dissipation factor and signal integrity in such materials is high and a need for low loss alternatives is critical. Such low Er's are impossible to obtain without new materials since the Er's of conventional FR4 epoxy and common fiber glass, as indicated above, are typically in the 4-6 range. The effective Er of such composite materials can usually be approximated by a simple weighted average of the Er of each individual component and its volume fraction contained in the composite. As further explained below, the above compositions are also often heavily weighted with brominated components, to assure the desired FR rating.
Substrates with fluoropolymer dielectric materials are known, including what are referred to as “pure” fluoropolymer substrates. One such example of a known material in use today is polytetrafluoroethylene (PTFE), which has an Er of approximately 2.0. However, using such a material alone in construction of a circuit board laminate has sometimes proven impractical, due to generally poor mechanical properties and chemical inertness of this material as well as high melting point and extremely high melt viscosity. One alternative is to use fluoropolymer as one of the components of a composite laminate material, such as the fiber in the reinforcing cloth. An example of this is the treated PTFE fabric prepreg produced by W. L. Gore and Associates, of Newark, Del. When this type of fabric is used to replace fiberglass in conventional epoxy/glass laminates, the Er drops to 2.8. However use of this fabric presents certain disadvantages. Because of the comparatively low modulus of pure PTFE, thin laminates made with these materials are not very rigid, and require special handling care. Also when laminates incorporating PTFE fabric are drilled, uncut PTFE fibers tend to protrude into the drilled holes and are difficult to remove. In order to obtain good plating adhesion, exposed PTFE surfaces must be treated using either an expensive, highly flammable chemical in a nitrogen atmosphere or by plasma processing, which must penetrate high aspect ratio through holes in order to obtain good plating adhesion. Certainly, one of the biggest disadvantages of PTFE fabric laminate is cost, not only the higher cost due to additional processing requirements and equipment modification, but also the considerable cost of purchasing the prepreg material itself. Further regarding fluoropolymer dielectric materials, in U.S. Pat. No. 5,055,342, entitled “Fluorinated polymeric composition, fabrication thereof and use thereof”, and which issued Oct. 8, 1991, there is described a fluorinated polymeric composition exhibiting a low dielectric constant and a low coefficient of thermal expansion containing a fluorinated polymeric material and a silica and/or quartz filler having a mean particle size of no greater than 7 microns. Layers of the above composition are obtained by applying the composition to a substrate and then heating the composition to a temperature sufficient to cause the composition to fuse. The filler material is selected from the group of silica, quartz, hollow micro-spheres and mixtures thereof.
The coefficient of thermal expansion (CTE) of a laminated dielectric material is another important factor with respect to substrate performance. It is desirable to closely match the coefficients of thermal expansion in the X and the Y directions of the dielectric material to that of the adjacent layers in order to prevent cracking of soldered joints linking the PCB to surface mounted devices, or to avoid separation of copper from the dielectric, or to prevent PCB warping. The X and Y direction CTE's are normally controlled by the glass fibers within the matrix. However these fibers do not control Z direction CTE. Z direction CTE must also be controlled in order to prevent cracking of copper plated through holes during heat cycling. Heat is generated in preparing or reworking solder connections, and in other manufacturing processes, and during current flow when the finished board is in operation or subjected to temperature variations during shipment or storage. One way to modify the CTE is by the use of fillers. Fillers may be linked to the matrix polymer to which these are added by the use of a coupling agent, often a silane. The coupling agent improves the bonding between the filler and the polymer, optimizing the interfacial bond area, which also improves both electrical and mechanical performance. Fillers of various types can affect the dielectric loss of a composite. The CTE of a prepreg dielectric material changes markedly when an inflection point called the glass transition temperature (Tg) is reached. Since the expansion rate of the dielectric material increases considerably when the Tg is reached, it is desirable for a dielectric material to have a high Tg in order to minimize stresses. Epoxy novolac based dielectric materials, for example, are considered to have a relatively high Tg, generally 150° C. or greater. Other characteristics associated with high Tg often include low moisture absorption and chemical resistance.
One known material which attempts to meet many of the above requirements is described in U.S. Pat. No. 5,126,192, entitled “Flame Retardant, Low Dielectric Constant Microsphere Filled Laminate”, which issued Jun. 30, 1992. According to the teachings of this patent, a resin/silane treated microsphere/carrier structure prepreg is prepared, B-stage cured, and then vacuum laminated. The impregnation mix is prepared by adding a predetermined quantity of microspheres to the resin/solvent mixture sufficient to result in a packing factor of, e.g., about 50% when the solvent is driven off. A low shear mixing technique must be used to avoid damaging the microspheres. Because these are spherical, the microspheres mix in readily and do not increase the viscosity of the solution to a point beyond which impregnation is difficult. The combination of microsphere size and packing factor enables the filled dielectric material to allegedly withstand the heat and pressure cycle of lamination without undergoing breakage of the hollow microspheres. According to this patent, less than 2% microsphere breakage was observed with lamination pressures up to 500 pounds per square inch (PSI). When breakage does occur, the largest microspheres generally collapse first. Hollow silica microspheres containing less than 2% sodium oxide, with 99% by population less than 40 microns in diameter, apparently provided by a company named Grace Syntactics, Inc. under the name “SDT 28”, are described as being acceptable. This same company's “SDT-60” microspheres, sized to 99% by population below 25 microns, are described as the preferred filler. The microspheres are treated with the silane-based coupling agent suitable for use with the specific resin. An especially suitable coupler for these formulations is also mentioned. One coupler mix is described as a combination of vinyl silane and amino silane, for best moisture resistance and acceptable wet dielectric loss performance. Silane resin allegedly binds the filler particles within the resin matrix and minimizes the volume of the interfacial areas between the resin matrix and the microspheres. The carrier/reinforcement material in this patent may be any known shell type reinforcement such as glass or polytetrafluoroethylene (PTFE). The carrier fabric selected depends mostly on the properties desired for the finished laminate. These include thickness, Er, CTE, and the intended product application. Carrier materials include woven and non-woven fiberglass and polymer fabrics and mats. Organic films such as polyimide film can also be used. Low Er fabrics such as D-glass, aramids such as Kevlar and Nomex, both registered trademarks of E. I. Dupont de Nemours and Company, poly p-phenylene benzobisthiazole, poly p-phenylene benzobisoxazole, Polyetheretherketone, aromatic polyesters, quartz, S-glass, and the like, can also be used in the formulation. The reinforcement can be in a cowoven or comingled form.
Another known material designed for use in circuitized substrates such as defined above and which is intended to also meet the above requirements of today's high-speed products is described in U.S. Pat. No. 6,207,595, entitled “Laminate And Method Of Manufacture Thereof”, which issued Mar. 27, 2001. In this patent, the dielectric layer's fabric material is made from a cloth member having a low enough content of particulates and a sufficient quantity of resin material to completely encase the cloth member including the particulates, so that the resin material extends beyond the highest protrusions of the cloth member (i.e. the fabric material is thicker and will pass a certain test standard (in '595, the known HAST level A test). Thus, the woven cloth is known to include a quantity of particulates, which term is meant in '595 to include dried film, excess coupler, broken filaments, and gross surface debris. A process is described where a sizing of polyvinyl alcohol, corn starch and a lubricant of oil is applied to the strands of fiber prior to weaving in order to improve the weaving process and minimize breakage of the strands. After weaving, the sizing is removed by a firing step to clean the filaments of lubricants and other materials. However, some sizing is randomly left behind as particulates. Encasing the woven cloth including the particulates is a quantity of hardened resin material. The resin may be an epoxy resin such as one often used for “FR4” composites. A resin material based on bismaleimide-triazine (BT) is also acceptable for the structure in this patent. More preferably, the resin is a phenolically hardenable resin material known in the PCB industry. This patent thus requires continuous fibers (those extending across the entire width (or length) of the dielectric layer except for possible inadvertent interruptions caused by drilling of the thru-holes needed in the final product, causing these fibers to become what might be called as “broken”. The aforementioned problem with fiber strands exposed to the holes is thus possible in this patent's process and resulting structure.
In U.S. Pat. No. 5,418,689, there is described a PCB product wherein the dielectric substrate can include a thermoplastic and/or thermosetting resin. Thermosetting polymeric materials mentioned in this patent include epoxy, phenolic base materials, polyimides and polyamides. Examples of some phenolic type materials include copolymers of phenol, resorcinol, and cresol. Examples of some suitable thermoplastic polymeric materials include polyolefins such as polypropylene, polysulfones, polycarbonates, nitrile rubbers, ABS polymers, and fluorocarbon polymers such as polytetrafluoroethylene, polymers of chlorotrifluoroethylene, fluorinated ethylenepropylene polymers, polyvinylidene fluoride and polyhexafluoropropylene. The dielectric materials may be molded articles of the polymers containing fillers and/or reinforcing agents such as glass filled polymers. “FR4” epoxy compositions that are employed in this patent contain 70-90 parts of brominated polyglycidyl ether of bisphenol-A and 10-30 parts of tetrakis (hydroxyphenyl) ethane tetraglycidyl ether cured with 3-4 parts of dicyandiamide, and 0.2-0.4 parts of a tertiary amine, all parts being parts by weight per hundred parts of resin solids. Another “FR4” epoxy composition may contain about 25 to about 30 parts by weight of a brominated digylcidyl ether of bisphenol-A having an epoxy equivalent weight of about 350 to about 450; about 10 to about 15% by weight of a brominated diglycidyl ether of bisphenol-A having an epoxy equivalent weight of approximately 600 to about 750 and about 55 to about 65 parts per weight of at least one epoxidized nonlinear novolak having at least 6 terminal epoxy groups; along with suitable curing and/or hardening agents. A still further “FR4” epoxy composition contains 70 to 90 parts of brominated polyglycidyl ether of bisphenol-A and 10 to 30 parts of tetrakis (hydroxyphenyl) ethane tetraglycidyl ether cured with 0.8-1 phr of 2-methylimidazole. Still other “FR4” epoxy compositions employ tetrabromobisphenol-A as the curing agent along with 2-methylimidazole as the catalyst.
In U.S. Pat. No. 6,323,436, PCBs are prepared by first impregnating a non-woven aramid chopped fiber mat or a thermoplastic liquid crystalline polymer (LCP) paper instead of the reinforcement typically used in the electronics industry, described in this patent as a woven glass fabric. The aramid reinforcement is comprised of a random (in-plane) oriented mat of p-aramid (poly(p-phenylene terephthalamide) fibers comprised of Kevlar (Kevlar is a registered trademark of E. I. DuPont de Nemours and Company), and has a dielectric constant of 4.0 as compared to 6.1 for standard E-glass cloth. The lower permittivity of the non-woven aramid reinforcement provides for faster signal propagation, allowing increased wiring density and less crosstalk, which becomes increasingly important for high I/O chips and miniaturization. Since the p-aramid fibers are transversely isotropic and have an axial CTE of about -3 to about -6 ppm/° C. when combined with a thermosetting resin, the final composite described in this patent is said to possess a CTE which can be controlled and adjusted to match that of silicon or semiconductor chips in the range of about 3 to about 10 ppm/° C. The thermoplastic liquid crystal polymer paper is a material called Vecrus (Vecrus is a registered trademark of Hoechst Celanese Corp.). LCP paper uses the company's Vectra polymer (Vectra also being a registered trademark of Hoechst Celanese Corp.). According to this patent, it has a dielectric constant of 3.25 and a dissipation factor of 0.024 at 60 Hz. The polymer paper has a UL94-V0 rating and an in-plane CTE of less than 10 ppm/° C. The alleged advantages of this material over the aramid mat are the lower dielectric constant and very low moisture absorption, less than 0.02%. The non-woven aramid or LCP paper is used in conjunction with a thermosetting resin to form the final composite substrate. Examples of thermosetting resins described as being useful in this patent include epoxy, cyanate ester, bismaleimide, bismaleimide-triazine, maleimide or combinations thereof. The resin-impregnated low CTE reinforcement is then partially cured to a “B”-stage to form the prepreg, and then the prepreg is cut, stacked, and laminated to form a subcomposite with exterior copper sheets.
Yet another type of dielectric materials known for use in circuitized substrates include those known as “expanded PTFE” materials, PTFE of course being the designate for polytetrafluoroethylene. A more common example of such material is the aforementioned Teflon, sold by E. I. DuPont de Nemours and Company. In U.S. Pat. No. 5,652,055, for example, there is described an adhesive sheet (or “bond film”) material suitable to serve as adhesive layers in a variety of adhesive applications, such as in circuit board laminates, multi-chip modules, and in other electrical applications. The adhesive sheet is described as being constructed from an expanded polytetrafluoroethylene (PTFE) material, such as that taught in U.S. Pat. No. 3,953,566. Preferably, the material is filled with an inorganic filler material and is constructed as follows. A ceramic filler is incorporated into an aqueous dispersion of dispersion-produced PTFE. The filler in small particle form is ordinarily less than 40 microns in size, and preferably less than 15 microns. The filler is introduced prior to co-coagulation in an amount that will provide 10 to 60%, and preferably 40 to 50% by weight filler in the PTFE, in relation to the final resin-impregnated composite. The filled PTFE dispersion is then co-coagulated, usually by rapid stirring. The coagulated filled PTFE is then added. The filled material is then lubricated with a common paste extrusion lubricant, such as mineral spirits or glycols, and then paste extruded. The extrudate is usually calendared, and then rapidly stretched to 1.2 times to 5000 times, preferably 2 times to 100 times, per this patent, at a stretch rate of over 10% per second at a temperature of between 35° C. and 327° C. The lubricant can be removed from the extrudate prior to stretching, if desired. The resulting expanded, porous filled PTFE is then imbibed with adhesive by dipping, calendaring, or doctor blading on a varnish solution of about 2% to 70% adhesive in solvent. The wet composite is then affixed to a tenter frame, and subsequently B-staged at or about 165° C. for 1 to 3 minutes. The resulting sheet adhesive thus obtained typically consists of: (a) 9 to 65 weight percent PTFE; (b) 9 to 60 weight percent inorganic filler, in the form of particulate; and (c) 5 to 60 weight percent adhesive imbibed within the porous structure of the filled PTFE web. Other types of expanded-PTFE substrate materials are described in U.S. Pat. Nos. 4,187,390 and 4,482,516, as well as others. U.S. Pat. No. 4,187,390 is particularly interesting because it delves substantially into both nodes and fibrils used as part of such substrate materials, breaking these down into such dimensional constraints as node height, node width, node length, and fibril length.
U.S. Pat. No. 4,634,631 describes a flexible circuit laminate including a microglass reinforced fluoropolymer layer sandwiched between a polyimide substrate and a copper conductive pattern. The glass reinforced fluoropolymer acts as a high bond strength adhesive between the polyimide and copper conductive pattern and, according to the authors, also contributes to improved dimensional stability as well as improved electrical performance. The described microglass content is between about 4 to about 30 weight percent, and more preferably about 20 weight percent glass. In the method described in this patent for making the flexible circuit laminate, the polyimide substrate undergoes a preferably alkaline microetching surface treatment, followed by rinsing, drying and lamination to the microglass reinforced fluoropolymer and copper layers.
In U.S. Pat. No. 4,849,284, there is described a ceramic filled fluoropolymer-based electrical substrate material for forming rigid printed wiring board substrate materials and integrated circuit chip carriers. According to the authors, the material exhibits improved electrical performance over other printed wiring board materials and circuit chip carriers, and the low coefficients of thermal expansion and compliant nature of these substrate materials result in improved surface mount reliability and plated through-hole reliability. The electrical substrate material comprises polytetrafluoroethylene filled with silica along with a small amount of microfiberglass. The ceramic filler (silica) is coated with a silane coating material which renders the surface of the ceramic hydrophobic and provides improved tensile strength, peel strength and dimensional stability.
In some known dielectric compositions, as mentioned above (e.g., the “FR4” dielectric material), bromine is used as one of the composition elements. Bromine is considered beneficial to provide moisture and flammability resistance and to assist in assuring a high glass transition temperature for the resulting structure. In one known composition, this material is believed to constitute approximately thirty percent (%) of the composition, by weight, in addition to bisphenol-A, a known industrial chemical used in epoxy resins (and other products), and epoxy cresol novolac resin.
The present invention represents a significant improvement over dielectric compositions such as those above which are then formed into dielectric layers for use in the production of circuitized substrates such as PCBs. One particularly significant feature of this invention is the provision of a dielectric material which includes two fluoropolymers, a low melting point fluoropolymer and a higher melting point fluoropolymer, in combination with two fillers, one with low thermal conductivity and the other a higher thermal conductivity. The resulting composition, when utilized as a dielectric material within a substrate, exhibits a low dielectric constant, a low coefficient of thermal expansion, and good thermal conductivity. Additional advantageous features of this composition will be defined in greater detail below. It is believed that such an invention will represent a significant advancement in the art.